Registers By Name

Symbol	Description
P	New register in Pandora chip set
p	Stuff added or changed in hires chips
H	New register in hires chips
h	Features added or changed in hires chips

A	Agnus / Alice chip
D	Denise / Lisa chip
P	Paula chip

W	Write
R	Read
ER	Early read. This is a DMA data transfer to RAM, from either the disk or from the blitter, Ram timing requires data to be on the bus earlier than microprocessor read cycles. These transfers are therefore initiated by Agnus timing, rather than a read address on the register address bus (RGA).

ADKCON

Name	Rev	Addr	Type	Chip	Description
ADKCON		09E	W	P	Audio, Disk, Uart, Control write
ADKCONR		010	R	P	Audio, Disk, Uart, Control read

Bits#	Use	Description
15	Set / Clear	Set/clear control bit.determines if bits written with a 1 get set or cleared. Bits written with a zero are always unchanged.
14-13	Precom 1 – 0
12	MFMPREC	(1 = MFM precomp / 0 = GCR precomp)
12	UARTBRK	Forces a UART break (clears TXD) if true
11	WORDSYNC	Enables disk read synchronizing on a word equal to DISK SYNC CODE, Located in address DSKSYNC (7E).
10	MSBSYNC	Enables disk read synchrinizing on the MSB (most signif bit) appl type GCR
09	FAST	Disk data clock rate control 1=fast(2us) 0=slow(4us) (Fast for MFM or 2us,slow for 4us GCR)
08	USE3PN	Use audio channel 3 to modulate nothing
07	USE2P3	Use audio channel 2 to modulate period of channel 3
06	USE1P2	Use audio channel 1 to modulate period of channel 2
05	USE0P1	Use audio channel 0 to modulate period of channel 1
04	USE3VN	Use audio channel 3 to modulate nothing
03	USE2V3	Use audio channel 2 to modulate volume of channel 3
02	USE1V2	Use audio channel 1 to modulate volume of channel 2
01	USE0V1	Use audio channel 0 to modulate volume of channel 1

Note:

If both period and volume aremodulated on the same channel, the period and volume will be alternated. First AUDxDAT word is used for V6-V0 of AUDxVOL. Second AUDxDAT word is used for P15-P0 of AUDxPER. This alternating sequence is repeated.

AUDxLCH

Name	Rev	Addr	Type	Chip	Description
AUDxLCH		0A0	W	A	Audio channel x location (high 5 bits) (old-3 bits)

AUDxLCL

Name	Rev	Addr	Type	Chip	Description
AUDxLCL		0A2	W	A	Audio channel x location (low 15 bits)

Note:

This pair of registers contains the 20 bit starting address(location) of audio channel x (x=0,1,2,3) DMA data. This is not a pointer reg and therfore only needs to be reloaded if a diffrent memory location is to be outputted.

AUDxLEN

Name	Rev	Addr	Type	Chip	Description
AUDxLEN		0A4	W	P	Audio channel x length

Note:

This reg contains the lentgh (number of words) of audio channel x DMA data.

AUDxPER

Name	Rev	Addr	Type	Chip	Description
AUDxPER	h	0A6	W	P	Audio channel x period.

Note:

This reg contains the period (rate) of audio channelx DMA data transfer.The minimum period is 124 clocks. This means that the smallest number that should be placed in this register is 124.

AUDxVOL

Name	Rev	Addr	Type	Chip	Description
AUDxVOL		0A8	W	P	Audio channel x volume.

Note:

This reg contains the volume setting for audio channel x.Bits 6,5,4,3,2,1,0 specify 65 linear volume levels as shown below.

Bits	Use
15 – 07	Not Used
06	Forces volume to max (64 ones, no zeros)
05 – 00	Sets one of the 64 levels (000000 = no output, 111111 = 63 ones, one zero)

AUDxDAT

Name	Rev	Addr	Type	Chip	Description
AUDxDAT		0AA	W	P	Audio channel x data.

Note:

This reg is the audio channel x (x=0,1,2,3) DMA data buffer. It contains 2 bytes of data (eachbyte is a twos complement signed integer) thatare outputed sequentially (with digital to analogconversion)to the audio output pins. With maximumvolume, each byte can drive the audio outputswith 0.8 volts(peak to peak,typ).

The audio DMAchannel controller automatically transfers datato this reg from RAM.

The processor can alsowrite directly to this reg. When the DMA data isfinished (words outputted=lentgh)and the data inthis reg has been used, an audio channel interruptrequest is set.

BEAMCON0

Name	Rev	Addr	Type	Chip	Description
BEAMCON0	h	1DC	W	A	Beam counter control bits

Bit#	Function
15	(Unused)
14	HARDDIS
13	LPENDIS
12	VARVBEN
11	LOLDIS
10	CSCBEN
9	VARVSYSEN
8	VARHSYSEN
7	VARBEAMEN
6	DUAL
5	PAL
4	VARCSYEN
3	(Unused, formerly BLANKEN)
2	CSYTRUE
1	VSYTRUE
0	HSYTRUE

HARDDIS	This bit is used to disable the hardwire vertical horizontal window limits. It is cleared upon reset.
LPENDIS	When this bit is a low and LPE (BPPCON0,BIT 3) is enabled, the light-pen latched value(beam hit position) will be read by VHPOSR, VPOSR and HHPOSR. When the bit is a high the light-pen latched value is ignored and the actual beam counter position is read by VHPOSR, VPOSR, and HHPOSR.
VARVBEN	Use the comparator generated vertical blank (from VBSTRT, VBSTOP) to run the internal chip stuff-sending RGA signals to Denise, starting sprites,resetting light pen. It also disables the hard stop on the vertical display window.
LOLDIS	Disable long line/short toggle. This is useful for DUAL mode where even multiples are wanted, or in any single display where this toggling is not desired.
CSCBEN	The variable composite sync comes out on the HSY pin, and the variable conosite blank comes out on the VSY pin. The idea is to allow all the information to come out of the chip for a DUAL mode display. The normal monitor uses the normal composite sync, and the variable composite sync &blank come out the HSY & VSY pins. The bits VARVSTEN & VARHSYEN (below) have priority over this control bit.
VARVSYEN	Comparator VSY -> VSY pin. The variable VSY is set vertically on VSSTRTT, reset vertically on VSSTOP, with the horizontal position for set set & reset HSSTRT on short fields (all fields are short if LACE = 0) and HCENTER on long fields (every other field if LACE = 1).
VARHSYEN	Comparator HSY -> HSY pin. Set on HSSTRT value, reset on HSSTOP value.
VARBEAMEN	Enables the variable beam counter comparators to operate (allowing diffrent beam counter total values) on the main horiz counter. It also disables hard display stops on both horizontal and vertical.
DUAL	Run the horizontal comparators with the alternate horizontal beam counter, and starts the UHRES pointer chain with the reset of this counter rather than the normal one. This allows the UHRES pointers to come out more than once in a horizontal line, assuming there is some memory bandwidth left (it doesn`t work in 6404004 interlace mode) also, to keep the two displays synced, the horizontal line lentghs should be multiples of each other. If you are amazingly clever, you might not need to do this.
PAL	Set appropriate decodes (in normal mode) for PAL. In variable beam counter mode this bit disables the long line/short line toggle- ends up short line.
VARCSYEN	Enables CSY from the variable decoders to come out the CSY (VARCSY is set on HSSTRT match always, and also on HCENTER match when in vertical sync. It is reset on HSSTOP match when VSY and on both HBSTRT & HBSTOP matches during VSY. A reasonable composite can be generated by setting HCENTER half a horiz line from HSSTRT, and HBSTOP at (HSSTOP–HSSTRT) before HCENTER, with HBSTRT at (HSSTOP–HSSTRT) before HSSTRT. HSYTRUE, VSYTRUE, CSYTRUE = These change the polarity of the HSY, VSY, & CSY* pins to HSY, VSY, & CSY respectively for input & output.

BLTxPTH

Name	Rev	Addr	Type	Chip	Description
BLTxPTH	h	050	W	A	Blitter Point to x (High 5 bits)

See also:

BLTxPTL

Name	Rev	Addr	Type	Chip	Description
BLTxPTL	h	052	W	A	Blitter Pointer to x (Low 15 bits)

Note:

This pair of registers (see also: BLTxPTH) contains the 20 bit address of Blitter source (X=A,B,C) or destination (x=D) DMA data.

This pointer must be preloaded with the starting address of the data to be processed by the blitter.

After the Blitter is finished it will contain the last data address (plus increment and modulo).

BLTxMOD

Name	Rev	Addr	Type	Chip	Description
BLTxMOD		064	W	A	Blitter Modulo x

Note:

This register contains the Modulo for Blitter source (x=A,B,C) or Dest (X=D). A Modulo is a number that is automatically added to the address at the end of each line, in order that the address then points to the start of the next line.

Each source or destination has it’s own Modulo, allowing each to be a different size, while an identical area of each is used in the Blitter operation.

BLTAFWM

Name	Rev	Addr	Type	Chip	Description
BLTAFWM		044	W	A	Blitter first word mask for source A

See also:

BLTALWM

Name	Rev	Addr	Type	Chip	Description
BLTALWM		046	W	A	Blitter last word mask for source A

Note:

The patterns in these two registers (see also: BLTAFWM) are “anded” with the first and last words of each line of data from Source A into the Blitter.

A zero in any bit overrides data from Source A. These registers should be set to all “ones” for fill mode or for line drawing mode.

BLTxDAT

Name	Rev	Addr	Type	Chip	Description
BLTxDAT		074	W	A	Blitter source x data reg

Note:

This register holds Source x (x=A,B,C) data for use by the Blitter. It is normally loaded by the Blitter DMA channel, however it may also be preloaded by the microprocessor.

BLTDDAT

Name	Rev	Addr	Type	Chip	Description
BLTDDAT		000	W	A	Blitter destination data register

Note:

This register holds the data resulting from each word of Blitter operation until it is sent to a RAM destination.

This is a dummy address and cannot be read by the micro. The transfer is automatic during Blitter operation.

BLTSIZE

Name	Rev	Addr	Type	Chip	Description
BLTSIZE		058	W	A	A Blitter start and size (Win/Width, Height)

Note:

This register contains the width and height of the blitter operation (in line mode Width must = 2, Height = line Length).

Writing to this register will start the Blitter, and should be done last, after all pointers and control registers have been initialized.

Bit#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
	H9	H8	H7	H6	H5	H4	H3	H2	H1	H0	W5	W4	W3	W2	W1	W0
H=Height=Vertical lines (10 Bits=1024 lines max)
W=Width=Horizontal pixels (6 Bits=64 words=1024 pixels max)

BLTCON0

Name	Rev	Addr	Type	Chip	Description
BLTCON0		040	W	A	Blitter control register 0
BLTCON0L	H	05A	W	A	Blitter control register 0 (Lower 8 bits). This is to speed up software – the upper bits are often the same.
BLTCON1	h	042	W	A	Blitter control register 1

Note:

These two control registers are used together to control blitter operations. There are 2 basic modes, are and line, which are selected by bit 0 of BLTCON1, as show below.

Bit#	BLTCON0	BLTCON1	Bit#	BLTCON0	BLTCON1
AREA MODE (Normal)			LINE MODE (Line Draw)
15	ASH3	BSH3	15	ASH3	BSH3
14	ASH2	BSH2	14	ASH2	BSH2
13	ASH1	BSH1	13	ASH1	BSH1
12	ASH0	BSH0	12	ASH0	BSH0
11	USEA	0	11	1	0
10	USEB	0	10	0	0
09	USEC	0	10	1	0
08	USED	0	10	1	0
07	LF7	DOFF	07	LF7	DPFF
06	LF6	0	06	LF6	SIGN
05	LF5	0	05	LF5	OFV
04	LF4	EFE	04	LF4	SUD
03	LF3	IFE	03	LF3	SUL
02	LF2	FCI	02	LF2	AUL
01	LF1	DESC	01	LF1	SING
00	LF0	LINE ( equ 0 )	00	LF0	LINE ( equ 1 )

Value	Description
ASH3-0	Shift value of A source
BSH3-0	Shift value of B source and line texture
USEA	Mode control bit to use source A
USEB	Mode control bit to use source B
USEC	Mode control bit to use source C
USED	Mode control bit to use destination D
LF7-0	Logic Function minterm select lines
EFE	Exclusive Fill Enable
IFE	Inclusive Fill Enable
FCI	Fill Carry Input
DESC	Descending (decrease address) control bit
LINE	Line mode control bit
SIGN	Line draw sign flag
OVF	Line/draw R/L word Overflow Flag
SUD	Line draw, Sometimes Up or Down ( equ AUD )
SUL	Line draw, Sometimes Up or Left
AUL	Line draw, Always Up or Left
SING	Line draw, Single bit per Horizontal line
DOFF	Disables the D output- for external ALUs. The cycle occurs normally, but the data bus is tristate (Hires chips only)

BLTSIZH

Name	Rev	Addr	Type	Chip	Description
BLTSIZH	h	05E	W	A	Blitter H Size Start (11 Bit Width)

Bit#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
	x	x	x	x	x	W10	W9	W8	W7	W6	W5	W4	W3	W2	W1	W0

See also:

BLTSIZV

Name	Rev	Addr	Type	Chip	Description
BLTSIZV	h	05C	W	A	Blitter Vertical Size (15 Bit Height)

Bit#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
	x	H14	H13	H12	H11	H10	H9	H8	H7	H6	H5	H4	H3	H2	H1	H0

Note:

These are the blitter size regs for blits larger than the earlier chips could accept. The original commands are retained for compatibility.

BLTSIZV should be written first, followed by BLTSIZH, which starts the blitter. BLTSIZV need not be re-written for subsequent bits if the vertical size is the same. Max size of blit 32k pixels * 32k lines, X’s should be written to 0 for upward compatibility.

BPLHDAT

Name	Rev	Addr	Type	Chip	Description
BPLHDAT	h	07A	W	A	Exteral Logic UHRES bit plane identifier

Note:

This is the number (sign extended) that is added to the UHRES bitplane pointer (BPLHPTL / BPLHPTH) every line, and then another 2 is added, just like the other modulos.

BPLHMOD

Name	Rev	Addr	Type	Chip	Description
BPLHMOD	h	1E6	W	A	Uhres bit plane modulo

Note:

This is the number (sign extended) that is added to the UHRES bitplane pointer (BPLHPTL, BPLHTH) every line, and then another 2 is added, just like the other modulos.

BPLHPTH

Name	Rev	Addr	Type	Chip	Description
BPLHPTH	h	1EC	W	A	UHRES (VRAM) bit plane pointer (High 5 Bits)

Note:

When UHRES is enabled, this pointer comes out on the 2nd ‘free’ cycle after the start of each horizontal line. It`s modulo is added every time it comes out. ‘free’ means priority above the copper and below the fixed stuff (audio,sprites….).

BPLHDAT comes out as an identifier on the RGA lines when the pointer address is valid so that external detectors can use this to do the special cycle for the VRAMs, The SHRHDAT gets the first and third free cycles.

BPLHPTL

Name	Rev	Addr	Type	Chip	Description
BPLHPTL	h	1EE	W	A	UHRES (VRAM) bit plane pointer (low 15 bits)

Note:

BPLHSTOP

Name	Rev	Addr	Type	Chip	Description
BPLHSTOP	p	1D6	W	A	UHRES bit plane Vertical stop

Bit#	Name
15	BPLHWRM
14-11	Unused
10-0	V10-V0

Note:

BPLHWRM = Swaps the polarity of ARW* when the BPLHDAT comes out so that external devices can detect the RGA and put things into memory (ECS and later versions).

BPLHSTRT

Name	Rev	Addr	Type	Chip	Description
BPLHSTRT	h	1D4	W	A	UHRES bit plane vertical start

Note:

This controls the line when the data fetch starts for the BPLHPTH, BPLHPTL Pointers. V10-V0 on DB10-0.

BPLxPTH

Name	Rev	Addr	Type	Chip	Description
BPLxPTH		0E0	W	A	Bit plane 1 Pointer (high 5 bits)
		0E4			Bit plane 2 Pointer (high 5 bits)
		0E8			Bit plane 3 Pointer (high 5 bits)
		0EC			Bit plane 4 Pointer (high 5 bits)
		0F0			Bit plane 5 Pointer (high 5 bits)
		0F4			Bit plane 6 Pointer (high 5 bits)
	p	0F8			Bit plane 7 Pointer (high 5 bits)
	p	0FC			Bit plane 8 Pointer (high 5 bits)

BPLxPTL

Name	Rev	Addr	Type	Chip	Description
BPLxPTL		0E2	W	A	Bit plane 1 Pointer (Low 15 Bits)
		0E6			Bit plane 2 Pointer (Low 15 Bits)
		0EA			Bit plane 3 Pointer (Low 15 Bits)
		0EE			Bit plane 4 Pointer (Low 15 Bits)
		0F2			Bit plane 5 Pointer (Low 15 Bits)
		0F6			Bit plane 6 Pointer (Low 15 Bits)
	p	0FA			Bit plane 7 Pointer (Low 15 Bits)
	p	0FE			Bit plane 8 Pointer (Low 15 Bits)

Note:

This pointer must be reinitialized by the processor or co-processor to point to the beginning of bit plane data every vertical blank time.

BPLxDAT

Name	Rev	Addr	Type	Chip	Description
BPLxDAT		110	W	A	Bit plane 1 data (Parallel to Serial convert)
		112			Bit plane 2 data (Parallel to Serial convert)
		114			Bit plane 3 data (Parallel to Serial convert)
		116			Bit plane 4 data (Parallel to Serial convert)
		118			Bit plane 5 data (Parallel to Serial convert)
		11A			Bit plane 6 data (Parallel to Serial convert)
	p	11C			Bit plane 7 data (Parallel to Serial convert)
	p	11E			Bit plane 8 data (Parallel to Serial convert)

Note:

These regs recieve the DMA data fetched from RAM by the bit plane address pointers described above. They may also be rewritten by either micro.

They act as a 8 word Parallel to Serial buffer for up to 8 memory ‘bit planes’. X=1-8 the parallel to serial conversion id triggered whenever bit plane #1 is written, indicing the completion of all bit planes for that word (16/32/64 pixels).

The MSB is output first, and is therefore always on the left.

BPLxMOD

Name	Rev	Addr	Type	Chip	Description
BPL1MOD		108	W	A	Bit plane modulo (Odd Planes)
BPL2MOD		10A	W	A	Bit plane modulo (Even Planes)

Note:

These registers contain the modulos for the odd and even bit planes. A modulo is a number that is automa- itcally added to the address at the end of each line, in order that the address then points to the start of the next line.

Since they have seperate modulos, the odd and even bit planes may have sizes that are different from each other, as well as different from the display window size. If scan-doubling is enabled, BPL1MOD serves as the primary bitplane modulos and BPL2MOD serves as the alternate.

Lines whose LSBs of beam counter and DIWSTRT match are designated primary, whereas lines whose LSBs don`t match are designated alternate.

BPLCON0

Name	Rev	Addr	Type	Chip	Description
BPLCON0	p	100	W	D	Bit plane control register (Misc. Control Bits)

Bit#	BPLCON0	Description
15	HIRES	HIRES = High resoloution (640200 / 640400 interlace) mode
14	BPU2	Bit plane use code 0000-1000 (NODE thru 8 inclusive)
13	BPU1
12	BPU0
11	HAM	Hold and modify mode, now using either 6 or 8 bit planes.
10	DPF	Dual playfield (PFI = odd FP2 = even bit planes) now available in all resoloutions. (If BPU=6 and HAM=0 and DPF=0 a special mode is defined that allows bitplane 6 to cause an intensity reduction of the other 5 bitplanes. The color register output selected by 5 bitplanes is shifted to half intensity by the 6th bit plane. This is called EXTRA-HALFBRITE Mode.
09	COLOR	Enables color burst output signal
08	GAUD	Genlock audio enable. This level appears on the ZD pin on denise during all blanking periods, unless ZDCLK bit is set.
07	UHRES	UltraHi-Res enables the UHRES pointers (for 1k*1k) (also needs bits in DMACON (hires chips only). Disables hard stops for vert, horiz display windows.
06	SHRES	Super Hi-Res mode (35ns pixel width)
05	BYPASS=0	Bitplanes are scrolled and prioritized normally, but bypass color table and 8 bit wide data appear on R(7:0).
04	BPU3=0	See above (BPU0/1/2)
03	LPEN	Light pen enable (Reset on Power-Up)
02	LACE	Interlace enable (Reset on Power-Up)
01	ERSY	External resync (HSYNC, VSYNC pads become inputs) (Reset on Power-Up)
00	ESCENA=0	When Low (Default), the following bits in BPLCON3 are disabled: BRDRBLNK BRDNTRAN ZDCLKEN BRDSPRT EXTBLKEN These 5 bits can always be set by writing to BPLCON3, however there effects are inhibited until ECSENA goes high. This allows rapid context switching between pre-ECS viewports and new ones.

BPLCON1

Name	Rev	Addr	Type	Chip	Description
BPLCON1	p	102	W	D	Bit plane control register (Horizontal, Scroll Counter)

Bit#	BPLCON1	Description
15	PF2H7=0	PF2Hx = Playfield 2 Horizontal Scroll Code, X = 0-7
14	PF2H6=0
13	PF2H1=0
12	PF2H0=0
11	PF1H7=0
10	PF1H6=0
09	PF1H1=0
08	PF1H0=0

07	PF2H5	PF1Hx = Playfield 1 horizontal scroll code, x=0-7 Where PFyH0 = LSB = 35ns SHRES pixel. Bits have been renamed, old PFyH0 now PFyH2, etc. Now that the scroll range has been quadrupled to allow for wider (32 or 64 bits) bitplanes.
06	PF2H4
05	PF2H3
04	PF2H2
03	PF1H5
02	PF1H4
01	PF1H3
00	PF1H2

BPLCON2

Name	Rev	Addr	Type	Chip	Description
BPLCON2	p	104	W	D	Bit plane Control Register (New Control Bits)

Bits#	BPLCON2	Description
15	X	Unused, but Set to 0 for Upward Compatibility!
14	ZDBPSEL2	3 Bit field which selects which bitplane is to be used for ZD when ZDBBPEN is set- 000 selects BB1 and 111 selects BP8.
13	ZDBPSEL1
12	ZDBPSEL0
11	ZDBPEN	Causes ZD pin to mirror bitplane selected by ZDBPSELx bits. This does not disable the ZD mode defined by ZDCTEN, but rather is “ORed” with it.
10	ZDCTEN	Causes ZD pin to mirror Bit #15 of the active entry in high color table. When ZDCTEN is Reset ZD reverts to mirroring color (0).
09	KILLEHB	Disables extra half brite mode.
08	RDRAM=0	Causes color table address to read the color table instead of writing to it.
07	SOGEN=0	When set causes SOG output pin to go high
06	PF2PRI	Gives playfield 2 priority over playfield 1.
05	PF2P2	Playfield 2 priority code (with resp. to sprites). Playfield 1 priority code (with resp. to sprites).
04	PF2P1
03	PF2P0
02	PF1P2
01	PF1P1
00	PF1P0

BPLCON3

Name	Rev	Addr	Type	Chip	Description
BPLCON3	p	106	W	D	Bit plane control register (Enhanced Features)

Bit#

BPLCON3

Description

BANK2=0

BANKx = Selects one of eight color banks, x = 0-2.

BANK1=0

BANK0=0

PF2OF2=0

Determine bit plane color table offset when playfield 2 has priority in dual playfield mode:

PF2OF1=1

PF20F			Affected Bitplane								Offset
2	1	0	8	7	6	5	4	3	2	1	( Decimal )
0	0	0	–	–	–	–	–	–	–	–	None
0	0	1	–	–	–	–	–	–	1	–	2
0	1	0	–	–	–	–	–	1	–	–	4
0	1	1	–	–	–	–	–	1	–	–	8 ( Default )
1	0	0	–	–	–	1	–	–	–	–	16
1	0	1	–	–	–	1	–	–	–	–	32
1	1	0	–	–	1	–	–	–	–	–	64
1	1	1	1	–	–	–	–	–	–	–	128

PF2OF0=1

LOCT=0

Dictates that subsequent color palette values will be written to a second 12- bit color palette, constituting the RGB low minus order bits.

Writes to the normal Hi-Monus order color palette automattically copied to the low order for backwards compatibility.

Unused, but Set to 0 for Upward Compability.

SPRES1=0

Determine resolution of all 8 sprites (x = 0 – 1):

SPRES1	SPRES0	Sprite Resolution
0	0	ECS defaults (LORES, HIRES=140ns, SHRES=70ns)
0	1	LORES (140ns)
1	0	HIRES (70ns)
1	1	SHRES (35ns)

SPRES0=0

BRDRBLNK=0

“Border area” is blanked instead of color 0. Disabled when ECSENA low.

BRDNTRAN=0

“Border area” is non minus transparant (ZD pin is low when border is displayed).

Disabled when ECSENA low.

Unused, but Set to 0 for Upward Compability.

ZDCLKEN=0

ZD pin outputs a 14MHz clock whose falling edge coincides with hires (7MHz) video data. this bit when set disables all other ZD functions. Disabled when ESCENA low.

BRDSPRT=0

Enables sprites outside the display window.

Disabled when ESCENA low.

EXTBLKEN=0

Causes BLANK output to be programmable instead of reflecting internal fixed decodes.

Disabled when ESCENA low.

BPLCON4

Name	Rev	Addr	Type	Chip	Description
BPLCON4	p	10C	W	D	Bit plane control register (Display Masks)

Bit#	BPLCON4	Description
15	BPLAM7=0	This 8 bit field is XOR`ed with the 8 bit plane color address, thereby altering the color address sent to the color table (x = 1 – 8)
14	BPLAM6=0
13	BPLAM5=0
12	BPLAM4=0
11	BPLAM3=0
10	BPLAM2=0
09	BPLAM1=0
08	BPLAM0=0
07	ESPRM7=0	4 Bit field provides the 4 high order color table address bits for even sprites: SPR0 SPR2 SPR4 SPR6 Default value is 0001 binary. (x = 7 – 4)
06	ESPRM6=0
05	ESPRM5=0
04	ESPRM4=1
03	OSPRM7=0	4 Bit field provides the 4 high order color table address bits for odd sprites: SPR1 SPR3 SPR5 SPR7 Default value is 0001 binary. (x = 7 – 4)
02	OSPRM6=0
01	OSPRM5=0
00	OSPRM4=1

CLXCON

Name	Rev	Addr	Type	Chip	Description
CLXCON		098	W	A	Collision control

Note:

This register controls which bitplanes are included (enabled) in collision detection, and their required state if included.

It also controls the individual inclusion of odd numbered sprites in the collision detection, by logically OR’ing them with their corresponding even numbered sprite. Writing to this register resets the bits in CLXCON2.

Bits#	Function	Description
15	ENSP7	Enable Sprite 7 (ORed with Sprite 6)
14	ENSP5	Enable Sprite 5 (ORed with Sprite 4)
13	ENSP3	Enable Sprite 3 (ORed with Sprite2)
12	ENSP1	Enable Sprite 1 (ORed with Sprite 0)
11	ENSP6	Enable bit plane 6 (match reqd. for collision
10	ENSP5	Enable bit plane 5 (match reqd. for collision
09	ENSP4	Enable bit plane 4 (match reqd. for collision
08	ENSP3	Enable bit plane 3 (match reqd. for collision
07	ENSP2	Enable bit plane 2 (match reqd. for collision
06	ENSP1	Enable bit plane 1 (match reqd. for collision
05	ENSP6	Match value for bit plane 6 collision
04	ENSP5	Match value for bit plane 5 collision
03	ENSP4	Match value for bit plane 4 collision
02	ENSP3	Match value for bit plane 3 collision
01	ENSP2	Match value for bit plane 2 collision
00	ENSP1	Match value for bit plane 1 collision

CLXCON2

Name	Rev	Addr	Type	Chip	Description
CLXCON2	P	10C	W	D	Extended collision control

This reg controls when bit planes 7 and 8 are included in collision detection, and there required state if included. Contents of this register are reset by a write to CLXCON.

BITS INITIALIZED BY RESET

Bits#	Function	Description
15-08		Unused
07	ENBP8	Enable bit plane 8 (match reqd. for collision)
06	ENBP7	Enable bit plane 7 (match reqd. for collision)
05-02		Unused
01	MVBP8	Match value for bit plane 8 collision
00	MVBP7	Match value for bit plane 7 collision

Note:

Disable bit planes cannot prevent collisions. Therefore if all bitplanes are disabled, collision will be continuous, regardless of the match values.

CLXDAT

Name	Rev	Addr	Type	Chip	Description
CLXDAT		00E	R	D	Collision data reg. (Read and Clear)

This address reads (and clears) the collision detection reg. The bit assignments are below.

Note:

Playfield 1 is all odd numbered enabled bit planes.
Playfield 2 is all even numbred enabled bit planes.

Bits#	Collision Registered
15	Unused
14	Sprite 4 (or 5) to Sprite 6 (or 7)
13	Sprite 2 (or 3) to Sprite 6 (or 7)
12	Sprite 2 (or 3) to Sprite 4 (or 5)
11	Sprite 0 (or 1) to Sprite 6 (or 7)
10	Sprite 0 (or 1) to Sprite 4 (or 5)
09	Sprite 0 (or 1) to Sprite 2 (or 3)
08	Playfield 2 to Sprite 6 (or 7)
07	Playfield 2 to Sprite 4 (or 5)
06	Playfield 2 to Sprite 2 (or 3)
05	Playfield 2 to Sprite 0 (or 1)
04	Playfield 1 to Sprite 6 (or 7)
03	Playfield 1 to Sprite 4 (or 5)
02	Playfield 1 to Sprite 2 (or 3)
01	Playfield 1 to Sprite 0 (or 1)
00	Playfield 2 to Playfield 2

COLORxx

Name	Rev	Addr	Type	Chip	Description
COLORxx		180-1BE	W		COLOR table xx

There 32 of these registers (xx=00-31) and together with the banking bits they address the 256 locations in the color palette. There are actually two sets of color regs, selection of which is controlled by the LOCT reg bit.

When LOCT = 0 the 4 MSB of red, green and blue video data are selected along with the T bit for genlocks the low order set of registers is also selected as well, so that the 4 bits- values are automatically extended to 8 bits.This provides compatibility with old software.

If the full range of palette values are desired, then LOCT can be set high and independant values for the 4 LSB of red, green and blue can be written. The low order color registers do not contain a transparency (T) bit.

The table below shows the color register bit usage.

Bit#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
LOCT=0	T	X	X	X	R7	R6	R5	R4	G7	G6	G5	G4	B7	B6	B5	B4
LOCT=1	X	X	X	X	R3	R2	R1	R0	G3	G2	G1	G0	B3	B2	B1	B0

Note:

T = TRANSPARENCY, R = RED, G = GREEN, B = BLUE, X = UNUSED

T bit of COLOR00 thru COLOR31 sets ZD_pin HI, When that color is selected in all video modes.

COPCON

Name	Rev	Addr	Type	Chip	Description
COPCON	h	02E	W	A	Coproccessor control register

This is a-1 bit register that when set true, allows the coprocessor to access the blitter hardware. This bit is cleared power on reset, so that the coprocessor cannot access the blitter hardware.

Bit#

Name

Function

CDANG

Co-processor danger mode. Allows coprocessor access to all RGA registers if true.

If 0, access to RGA>7E.
On old chips access to only RGA>3E if CDANG=1.

See VPOSR

COPJMP1

Name	Rev	Addr	Type	Chip	Description
COPJMP1		088	S	A	Coprocessor restart at first location

See:

COPJMP2

Name	Rev	Addr	Type	Chip	Description
COPJMP2		08A	S	A	Coprocessor restart at second location

Note:

These address are strobe address, that when written to cause the coprocessor to jump indirect useing the address contained in the first or second location register described below.

The coprocessor itself can write to these address, causeing it`s own jump indirect.

COP1LCH

Name	Rev	Addr	Type	Chip	Description
COP1LCH	h	080	W	A	A Coprocessor first location register (High 5 bits) (Old 3 bits)
COP1LCL		082	W	A	A Coprocessor first location register (Low 15 bits)
COP2LCH	h	084	W	A	A Coprocessor second location register (High 5 bits) (Old 3 bits)
COP2LCL		086	W	A	A Coprocessor second location register (Low 15 bits)

These regs contain the jump addresses described in COPINS.

COPINS

Name	Rev	Addr	Type	Chip	Description
COPINS		08C	W	A	Coprocessor instruction fetch identify

This is a dummy address that is generated by the coprocessor whenever it is loading instructions into its own instruction register. This actually occurs every coprocessor cycle except for the second (IR2) cycle of the MOVE instruction.

The three types of instructions are shown below.

MOVE: Move immediate to destination.

WAIT: Wait until beam counter is equal to, or greater than. (Keeps co-processor off of bus until beam position has been reached)

SKIP: Skip if beam counter is equal to, or greater than. (Skips following MOVE instruction unless beam position has been reached).

Bit#	IR1	IR2	IR1	IR2	IR1	IR2
	MOVE		WAIT UNTIL		SKIP IF
15	X	RD15	VP7	BFD	VP7	BFD
14	X	RD14	VP6	VE6	VP6	VE6
13	X	RD13	VP5	VE5	VP5	VE5
12	X	RD12	VP4	VE4	VP4	VE4
11	X	RD11	VP3	VE3	VP3	VE3
10	X	RD10	VP2	VE2	VP2	VE2
09	X	RD09	VP1	VE1	VP1	VE1
08	DA8	RD08	VP0	VE0	VP0	VE0
07	DA7	RD07	HP8	HE8	HP8	HE8
06	DA6	RD06	HP7	HE7	HP7	HE7
05	DA5	RD05	HP6	HE6	HP6	HE6
04	DA4	RD04	HP5	HE5	HP5	HE5
03	DA3	RD03	HP4	HE4	HP4	HE4
02	DA2	RD02	HP3	HE3	HP3	HE3
01	DA1	RD01	HP2	HE2	HP2	HE2
00	0	RD00	1	0	1	1

Value	Description
IR1	First instruction register
IR2	Second insturction register
DA	Destination address for MOVE instruction.Fetched during IR1 time,used during IR2 time on RGA bus.
RD	RAM Data moved by MOVE instruction at IR2 time directly from RAM to the address given by the DA field.
VP	Vertical beam position comparison bit.
HP	Horizontal beam position comparison bit.
VE	Enable comparison (Mask Bit).
HE	Enable comparison (Mask Bit).

* Note:

BFD

Blitter finished disable. When this bit is true, the blitter finished flag will have no effect on the coprocessor. When this bit is zero the blitter finished flag must be true (in addition to the rest of the bit comparisons) before the coprocessor can exit from it`s wait state, or skip over an instruction.

Note that the V7 comparison cannot be masked.

Note:

The coprocessor is basically a 2 cycle machine that requests the bus only during odd memory cycles. (4 memory cycles per in) It has priority over the blitter and micro. There are only three types of instructions, MOVE immediate, WAIT until ,and SKIP if.

All instructions require 2 bus cycles (and two instruction words).Since only the odd bus cycles are requested, 4 memory cycle times are required per instruction. (memory cycles are 280 ns).

There are two indirect jump registers COP1LCH and COP2LC. These are 20 bit pointer registers whose contents are used to modify program counter for initalization or jumps.

They are transfered to the program counter whenever strobe address COPJMP1 or COPJMP2 are written. In addition COP1LC is automatically used at the beginning of each vertical blank time.

It is important that one of the jump registers be initalized and it`s jump strobe address hit, after power up but before coprocessor DMA is initalized.T his insures a determined startup address, and state.

DDFSTRT

Name	Rev	Addr	Type	Chip	Description
DDFSTRT			W	A	Display data fetch start(Horizontal Position)
DDFSTOP			W	A	Display data fetch stop (Horizontal Position)

These registers control the horizontal timing of the beginning and end of the bit plane DMA timing display data fetch.

The vertical bit plane DMA timing is identical to the display windows described above. The bit plane Modulos are dependent on the bit plane horizontal size, and on this data fetch window size.

Bit#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Register Bit Assignment
Use	X	X	X	X	X	X	X	H8	H7	H6	H5	H4	H3	H2	X	–

(X bits should always be driven with 0 to maintain upward compatability)

The tables below show the start and stop timing for different register contents

Purpose	H8	H7	H6	H5	H4
DDFSTRT (Left edge of display data fetch)
Extra Wide (Max)	0	0	1	0	1

Wide	0	0	1	1	0

Normal	0	0	1	1	1

Narrow	0	1	0	0	0

Purpose	H8	H7	H6	H5	H4
DDFSTOP (Right edge of display data fetch)
Narrow	1	1	0	0	1

Normal	1	1	0	1	0

Wide (Max)	1	1	0	1	1

Note:

These numbers will vary with variable beam counter mode set:

(The maxes and mins, that is)

DIWSTRT

Name	Rev	Addr	Type	Chip	Description
DDFSTRT	08E		W	A D	Display Window Start (Upper left vertical / Horizontal position)
DDFSTOP	090		W	A D	Display Window Stop (Lower right Vertical / Horizontal position)

These registers control the display window size and position, by locating the upper left and lower right corners.

Bit#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Use	V7	V6	V5	V4	V3	V2	V1	V0	H9	H8	H7	H6	H5	H4	H3	H2

Note:

DIWSTRT is vertically restricted to the upper 2/3 of the display (v8=0),and horizontally restricted to the left 3/4 of the display (H8=0).* * Poof..

(see DIWHIGH for exceptions)

DIWHIGH

Name	Rev	Addr	Type	Chip	Description
DIWHIGH	p	1E4	W	A D	Display Window upper Bits for Start / Stop

Note:

This is an added register for Hires chips, and allows larger Start / Stop ranges. If it is not written, the above (DIWSTRT, DIWSTOP) description holds.

If this register is written, direct Start / Stop positions anywhere on the screen. It doesn`t affect the UHRES pointers.

Bit#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
	X	X	H10	H1	H0	V9	V8	X	X	H10	H1	H0	V10	V9	V8
	(Stop)								(Start)

Take care (X) bits should always be written to 0 to maintain upwards compatibility.

H1 and H0 values define 70ns amd 35ns increments respectively, and new LISA bits.

Note:

In all 3 display window registers, horizontal bit positions have been renamed to reflect HIRES pixel increments, e.g. what used to be called H0 is now referred to as H2.

DMACON

Name	Rev	Addr	Type	Chip	Description
DMACON		096	W	A D P	DMA control Write (Clear or Set)
DMACONR		002	R	A P	DMA control (and Blitter status) Read

This register controls all of the DMA channels, and contains Blitter DMA status Bits.

Bit#	Function	Description
15	SET / CLR	Set/Clear control bit. Determines if bits written wit a 1 get set or cleared. Bits written witn a zero are unchanged.
14	BBUSY	Blitter busy status bit (Read only)
13	BZERO	Blitter logic zero status bit. (Read only)
12	X
11	X
10	BLTPRI	Blitter DMA prioiry over CPU micro, also called “blitter nasty”. Disables /BLS pin, preventing micro from stealing any bus cycles while blitter DMA is running
09	DMAEN	Enable all DMA below (also UHRES DMA)
08	BPLEN	Bit plane DMA enable
07	COPEN	Co-processor DMA enable
06	BLTEN	Blitter DMA enable
05	SPREN	Sprite DMA enable
04	DSKEN	Disk DMA enable
03	AUD3EN	Audio chanel 3 DMA enable
02	AUD2EN	Audio chanel 2 DMA enable
01	AUD1EN	Audio chanel 1 DMA enable
00	AUD0EN	Audio chanel 0 DMA enable

DSKPTH

Name	Rev	Addr	Type	Chip	Description
DSKPTH	h	020	W	A	Disk pointer (High 5 Bits) (Old 3 Bits)
DSKPTL		022	W	A	Disk pointer (Low 15 Bits)

This pair of registers contains the 20 bit address of disk DMA data. These address registers must be initalized by the processor or co-processor before disk DMA is enabled.

DSKLEN

Name	Rev	Addr	Type	Chip	Description
DSKLEN		024	W	P	Disk length

Bit#	Function	Description
15	Disk DMA Enable	Disk DMA enable
14	WRITE/td>	Disk Write ( RAM or Disk ) if Set to 1
13-0	LENGTH	Length ( # of words ) of DMA data.

DSKDAT

Name	Rev	Addr	Type	Chip	Description
DSKDAT		026	W	P	Disk DMA Data Write

DSKDATR

Name	Rev	Addr	Type	Chip	Description
DSKDATR		008	ER	P	Disk DMA Data Read (Early Read dummy address)

This register is the disk-DMA data buffer.It contains 2 bytes of data that are either sent to (Write) or received from (Read) the disk.

The DMA controller automatically transfers data to or from this register and RAM, and when the DMA data is finished ( Length=0 ) it causes a disk block interrupt.

See interrupts below.

DSKBYTR

Name	Rev	Addr	Type	Chip	Description
DSKBYTR		01A	R	p	Disk data byte and status read

This register is the Disk-Microrocessor data buffer. Data from the disk (in read mode) is leaded into this register one byte at a time, and bit 15 ( DSKBYT ) is set true.

Bit#	Function	Description
15	DSKBYT	Disk Byte Ready ( Reset on Read )
14	DMAON	DMAEN ( DKSLEN ) & DMAEN ( DMACON ) & DSKEN ( DMACON )
13		Mirror of bit 14 ( WRITE ) in DSKLEN
12	WORDEQUAL	This bit true only while DSKSYNC register equals the data from disk
11-08	0	Unused
07-00	DATA	Disk Byte Data

DSKSYNC

Name	Rev	Addr	Type	Chip	Description
DSKSYNC		07E	W	P	Disk Sync Register, the match code for disk read synchronization. See ADKCON Bit 10

FMODE

Name	Rev	Addr	Type	Chip	Description
FMODE	P	1FC	W		Memory Fetch Mode

This register controls the fetch mechanism for different types of Chip RAM accesses as shown below.

Bit#	Function	Description
15	SSCAN	Global enable for sprite scan-doubling.
14	BSCAN	Enables the use of 2nd P/F modulus on an alternate line basis to support bitplane scan-doubling.
13-04		Unused
03	SPAGEM	Sprite page mode (double CAS)
02	SPR32	Sprite 32 bit wide mode
01	BPAGEM	Bitplane Page Mode (double CAS)
00	BPL32	Bitplane 32 bit wide mode

BPAGEM	BPL32	Bitplane Fetch	Increment	Memory Cycle	Bus Width
0	0	By 2 Bytes	( As before )	Normal CAS	16
0	1	By 4 Bytes		Normal CAS	32
1	0	By 4 Bytes		Double CAS	16
1	1	By 8 Bytes		Double CAS	32

SPAGEM	SPR32	Sprite Fetch	Increment	Memory Cycle	Bus Width
0	0	By 2 Bytes	( As before )	Normal CAS	16
0	1	By 4 Bytes		Normal CAS	32
1	0	By 4 Bytes		Double CAS	16
1	1	By 8 Bytes		Double CAS	32

HBSTOP

Name	Rev	Addr	Type	Chip	Description
HBSTOP		1C6	W	D	Horizontal STOP position
HBSTRT		1C4	W	D	Horizontal START position

Bits 7-0 contain the stop and start positions, respectively, for programed horizontal blanking in 280ns increments.

Bits 10-8 provide a fine position control in 35ns increments.

Bit#	Function	Description
15-11	X	Unused
10	H1	140ns
09	H1	70ns
08	H0	35ns
07	H10	35840ns
06	H9	17920ns
05	H8	8960ns
04	H7	4480ns
03	H6	2240
02	H5	1120ns
01	H4	560ns
00	H3	280ns

HCENTER

Name	Rev	Addr	Type	Chip	Description
HCENTER	H	1E2	W	A	Horizontal position (CCKs) of VSYNC on long field

This is necessary for interlace mode with variable beam counters. See BEAMCON0 for when it affects chip outputs.

See HTOTAL for Bits.

HHPOSR

Name	Rev	Addr	Type	Chip	Description
HHPOSR	H	1DA	R	A	DUAL mode Hi-Res Hbeam counter Read
HHPOSW	H	1D8	W	A	DUAL mode Hi-Res Hbeam counter Write

This the secondary beam counter for the faster mode, triggering the UHRES pointers & doing the comparisons for HBSTRT, HBSTOP, HTOTAL, HSSRT, HSSTOP.

See HTOTAL for bits.

HSSTOP

Name	Rev	Addr	Type	Chip	Description
HSSTOP	H	1C2	W	A	Horizontal line position for SYNC stop

Sets # of colour clocks for sync stop ( HTOTAL for Bits )

HSSTRT

Name	Rev	Addr	Type	Chip	Description
HSSTRT	H	1DE	W	A	Horizontal line position for HSYNC start

Sets # of colour clocks for sync start ( HTOTAL for Bits ).

See BEAMCON0 for details of when these 2 are active.

HTOTAL

Name	Rev	Addr	Type	Chip	Description
HTOTAL	H	1C0	W	A	Highest colour clock count in horizontal line

Bit#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Bit#	X	X	X	X	X	X	X	X	H8	H7	H6	H5	H4	H3	H2	H1

X`s should be driven to 0 for upward compatibility!

Horizontal line has theis many + 1 280ns increments. If the PAL bit & LOLDIS are not High, long line/skort line toggle will occur, and there will be this many +2 every other line.

Active if VARBEAMEN = 1 or DUAL + 1.

INTENA

Name	Rev	Addr	Type	Chip	Description
INTENA		09A	W	P	Interrupt Enable Bits (Clear or Set Bits)
INTENAR		01C	R	P	Interrupt Enable Bits (Read)

Bit#	Function	Level	Description
15	SET / CLR
14	INTEN		Master Interrupt (Enable only, no request)
13	EXTER	6	External Interrupt
12	DSKSYN	5	Disk sync register ( DSKSYNC ) matches disk
11	RBF	5	Serial Port Receive Buffer Full
10	AUD3	4	Audio Channel 3 block finished
09	AUD2	4	Audio Channel 2 block finished
08	AUD1	4	Audio Channel 1 block finished
07	AUD0	4	Audio Channel 0 block finished
06	BLIT	3	Blitter has finished
05	VERTB	3	Start of Vertical Blank
04	COPER	3	Co-processor
03	PORTS	2	I / O Ports and Timers
02	SOFT	1	Reserved for Software Interrupt
01	DSKBLK	1	Disk Block Finished
00	TBE	1	Serial Port Trasmit Buffer Empty

JOYxDAT

Name	Rev	Addr	Type	Chip	Description
JOY0DAT		00A	R	D	Joystick / Mouse 0 data ( Left vertical / Horizontal )
JOY1DAT		00C	R	D	Joystick / Mouse 1 data ( Right vertical / Horizontal )

Note:

These addresses each read a 16 bit register.

These in turn are loaded from the MDAT serial stream and are clocked in on the rising edge of SCLK. MLD output is used to parallel load the external parallel-to-serial converter.

This in turn is loaded with the 4 quadrature inputs from each of two game controller ports (8 total) plus 8 miscellaneous control bits which are new for LISA and can be read in upper 8 bits of LISAID.

Bit#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
JOY0DAT	Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y0	X7	X6	X5	X4	X3	X2	X1	X0
JOY1DAT	Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y0	X7	X6	X5	X4	X3	X2	X1	X0

0=LEFT CONTROLLER PAIR
1=RIGHT CONTROLLER PAIR.
(4 counters total).

The bit usage for both left and right addresses is shown below. Each 6 bit counter ( Y7 – Y2 ,X7 – X2 ) is clocked by 2 of the signals input from the mouse serial stream.

Starting with first bit recived:

Serial#	Bit Name	Description
0	M0H	JOY0DAT Horizontal Clock
1	M0HQ	JOY0DAT Horizontal Clock ( Quadrature )
2	M0V	JOY0DAT Vertical Clock
3	M0VQ	JOY0DAT Vertical Clock ( Quadrature )
4	M1H	JOY1DAT Horizontall Clock
5	M1HQ	JOY1DAT Horizontal Clock ( Quadrature )
6	M1V	JOY1DAT Vertical Clock
7	M1VQ	JOY1DAT Vertical Clock ( Quadrature )

Bits 1 and 0 of each counter ( Y1 – Y0, X1 – X0 ) may be read to determine the state of the related input signal pair.

This allows these pins to double as joystick switch inputs. Joystick switch closures can be deciphered as follows:

Directions	Pin #	Counter Bits
Forward	1	Y1 xor Y0 ( BIT#09 xor BIT#08 )
Left	2	Y1
Back	3	X1 xor X0 ( BIT#01 xor BIT#00 )
Right	4	X1

JOYTEST

Name	Rev	Addr	Type	Chip	Description
JOYTEST		036	W	D	Write to all 4 Joystick / Mouse counters at once.

Mouse Counter Write Test Data
Bit#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
JOY0DAT	Y7	Y6	Y5	Y4	Y3	Y2	–	–	X7	X6	X5	X4	X3	X2	–	–
JOY1DAT	Y7	Y6	Y5	Y4	Y3	Y2	–	–	X7	X6	X5	X4	X3	X2	–	–

LISAID

Name	Rev	Addr	Type	Chip	Description
LISAID	H	07C	R	D	Denise/Lisa (Video Uut Chip) Revision Level

The original Denise ( 8362 ) does not have this register, so whatever value is left over on the bus from the last cycle will be there. ECS Denise ( 8373 ) returns hex (FE) in the lower 8 bits.

Lisa returns hex ( F8 ). The upper 8 bits of this Register are loaded from the serial mouse bus, and are reserved for future hardware implentation.

The 8 low-order bits are encoded as follows:

Bit#	Description
07-04	Lisa/Denise/ECS Denise Revision level(decrement to bump revision level, hex F represents 0th rev. level).
03	Maintain as a 1 for future generation
02	When low indicates AA feature set (LISA)
01	When low indicates ECS feature set (LISA or ECS DENISE)
00	Maintain as a 1 for future generation

POTxDAT

Name	Rev	Addr	Type	Chip	Description
POT0DAT	h	012	R	P	Pot counter data left pair (Vertical, Horizontal)
POT1DAT	h	014	R	P	Pot counter data right pair (Vertical, Horizontal)

These addresses each read a pair of 8 bit pot counters. ( 4 counters total ). The bit assignment for both addresses is shown below.

The counters are stopped by signals from 2 controller connectors ( Left – Right ) with 2 pins each.

Bit#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
RIGHT	Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y0	X7	X6	X5	X4	X3	X2	X1	X0
LEFT	Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y0	X7	X6	X5	X4	X3	X2	X1	X0

Loc.	Dir.	Sym	Pin	Pin
Connectors				PAULA
RIGHT	Y	RY	9	33
RIGHT	X	RX	5	32
LEFT	Y	LY	9	36
LEFT	X	LX	5	35

With normal ( NTSC or PAL ) horiz. line rate, the pots will give a full scale ( FF ) reading with about 500kohms in one frame time.

With proportionally faster horiz line times, the counters will count proportionally faster. This should be noted when doing variable beam displays.

POTGO

Name	Rev	Addr	Type	Chip	Description
POTGO		034	W	P	Pot port (4 Bit) bi-direction and data, and pot counter start.

POTINP

Name	Rev	Addr	Type	Chip	Description
POTINP		016	R	P	Pot pin data Read

This register controls a 4 bit bi-direction I/O pors that shares the same 4 pins as the 4 pot counters above.

Bit#	Function	Description
15	OUTRY	Output enable for Paula pin 33
14	DATRY	I/O data Paula pin 33
13	OUTRX	Output enable for Paula pin 32
12	DATRX	I/O data Paula pin 32
11	OUTLY	Out put enable for Paula pin 36
10	DATLY	I/O data Paula pin 36
09	OUTLX	Output enable for Paula pin 35
08	DATLX	I/O data Paula pin 35
07-01		Unused
00	START	Start pots ( dump capacitors, start counters )

REFPTR

Name	Rev	Addr	Type	Chip	Description
REFPTR		028	W	A	Refresh pointer

This register is used as a dynamic RAM refresh address generator. It is writeable for test purposes only, and should never be written by the microprocesor.

SERDAT

Name	Rev	Addr	Type	Chip	Description
SERDAT		030	W	P	Serial port data and stop Bits Write.

This address writes data to a transmit data buffer. Data from this buffer is moved into a serial shift register for output transmission whenever it is empty.

This sets the interrupt request TBE ( Transmit Buffer Empty ). A stop bit must be provided as part of the data word. The length of the data word is set by the position of the stop bit.

Bit#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
USE	0	0	0	0	0	0	S	D8	D7	D6	D5	D4	D3	D2	D1	D0

Note:

S = Stop bit =1
D = Data bits

SERDATR

Name	Rev	Addr	Type	Chip	Description
SERDATR		018	R	P	Serial port data and status read.

This address reads data from a recive data buffer. Data in this buffer is loaded from a receiving shift register whenever it is full. Several interrupt request bits are also read at this address, along with the data as shown below.

Bit#	Function	Description
15	OVRUN	Serial port receiver overun
14	RBF	Serial port receive buffer full (mirror)
13	TBE	Serial port transmit buffer empty (mirror)
12	TSRE	Serial port transmit shift register empty
11	RXD	RXD pin receives UART serial data for direct bit test by the micro.
10	X	Unused
09	STP	Stop bit
08	STP-DB8	Stop bit if LONG, data bit if not.
07	DB7	Stop bit
06	DB6	Stop bit
05	DB5	Stop bit
04	DB4	Stop bit
03	DB3	Stop bit
02	DB2	Stop bit
01	DB1	Stop bit
00	DB0	Stop bit

SERPER

Name	Rev	Addr	Type	Chip	Description
SERPER		032	W	P	Serial port Period and Control.

This register contains the control bit LONG reffered to above, and a 15 bit number defining the serial port Baud rate.

If this number is N, then the baud rate is 1 bit every ( N+1 ) *.2794 microseconds.

Bit#	Function	Description
15	LONG	Defines serial receive as 9 bit word.
14-00	RATE	Defines baud rate = 1 / ( ( N+1 ) *.2794 microseconds)

SPRHDAT

Name	Rev	Addr	Type	Chip	Description
SPRHDAT	H	078	W	A	External Logic UHRES sprite identifier and data

This identifies the cycle when this pointer address is on the bus accessing the memory.

SPRHPTH

Name	Rev	Addr	Type	Chip	Description
SPRHPTH	H	1E8	W	A	UHRES sprite pointer ( High 5 Bits )
SPRHPTH	H	1EA	W	A	UHRES sprite pointer ( Low 15 Bits )

This pointer is activated in the 1st and 3rd ‘free’ cycles ( see BPLHPTH, BPLHPTL ) after horizontal line start. It increments for the next line.

SPRHSTOP

Name	Rev	Addr	Type	Chip	Description
SPRHSTOP	H	1D2	W	A	UHRES sprite vertical display stop

Bit#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
SPRHWRM	X	X	X	X	X	V10	V9	V8	V7	V6	V5	V4	V3	V2	V1	V0

SPRHWRM = Swaps the polarity of ARW* when the SPRHDAT comes out so that external devices can detect the RGA and put things into memory.

( ECS and later chips only )

SPRHSTRT

Name	Rev	Addr	Type	Chip	Description
SPRHSTRT	H	1D0	W	A	UHRES sprite vertical display start

Bit#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
	X	X	X	X	X	V10	V9	V8	V7	V6	V5	V4	V3	V2	V1	V0

SPRxPTH

Name	Rev	Addr	Type	Chip	Description
SPRxPTH		120	W	A	Sprite X Pointer ( High 5 Bits )
SPRxPTL		122	W	A	Sprite X Pointer ( Low 15 Bits )

This pair of registers contains the 20 bit address of sprite x ( x = 0, 1 , 2 , 3 , 4 , 5, 6 and 7 ) DMA data. These address registers must be initalized by the processor or coprocessor every vertical blank time.

SPRxPOS

Name	Rev	Addr	Type	Chip	Description
SPRxPOS		140	W	A D	Sprite x Vertical / Horizontal start position data.

Bit#

Function

Description

15-08

SV7-SV0

Start vertical value. High Bit ( SV8 ) is in SPRxCTL register below.

07-00

SH10-SH3

Sprite horizontal start value. Low order 3 bits are in SPRxCTL register below. If SSCAN2 bit in FMODE is set, then disable SH10 horizontal coincidence detect.

This bit is then free to be used by ALICE as an individual scan double enable.

SPRxCTL

Name	Rev	Addr	Type	Chip	Description
SPRxCTL	p	142	W	A D	Sprite position and control data

Bit#	Function	Description
15-08	EV7-EV0	End ( stop ) vertical value. Low 8 Bits
07	ATT	Sprite Attach Control Bit ( odd sprites only )
06	SV9	Start vertical value 10th Bit.
05	EV9	End ( Stop ) vertical value 10th Bit
04	SH1=0	Start horizontal value, 70nS increment
03	SH0=0	Start horizontal value 35nS increment
02	SV8	Start vertical value 9th Bit
01	EV8	End ( stop ) vertical value 9th Bit
00	SH2	Start horizontal value, 140nS increment

These 2 registers work together as position, size and feature sprite control registers. They are usually loaded by the sprite DMA channel, during horizontal blank, however they may be loaded by either processor any time.

Writing to SPRxCTL disables the corresponding sprite.

SPRxDAT

Name	Rev	Addr	Type	Chip	Description
SPRxDATA		144	W	D	Sprite X Image Data Register A
SPRxDATB		146	W	D	Sprite X Image Data Register B

These registers buffer the sprite image data. They are usually loaded by the sprite DMA channel but may be loaded by either processor at any time.

When a horizontal coincidence occurs the buffers are dumped into shift registers and serially outputed to the display, MSB first on the left.

Note:

Writing to the A buffer enables ( arms ) the sprite. Writing to the SPRxCTL registers disables the sprite.

If enabled, data in the A and B buffers will be output whenever the beam counter equals the sprite horizontal position value in the SPRxPOS register.

In lowres mode, 1 sprite pixel is 1 bitplane pixel wide.

In HRES and SHRES mode, 1 sprite pixel is 2 bitplane pixels. The DATB bits are the 2SBs (worth 2) for the color registers, and MSB for SHRES. DATA bits are LSBs of the pixels.

STREQU

Name	Rev	Addr	Type	Chip	Description
STREQU		038	S	D	Strobe for horizontal sync with VB ( Vertical Blank) and EQU
STRVBL		03A	S	D	Strobe for horiz sync with VB
STRHOR		03C	S	D P	Strobe for horizontal sync
STRLONG	h	03E	S	D

One of the first 3 strobe addresses above, it is placed on the RGA bus during the first refresh time slot of every other line, to identify lines with long counts ( 228 – NTSC, HTOTAL + 2 – VARBEAMEN = 1 Hi-Res chips only ).

There are 4 refresh time slots and any not used for strobes will leave a null ( 1FE ) address on the RGA bus.

VBSTOP

Name	Rev	Addr	Type	Chip	Description
VBSTOP	H	1CE	W	A	Vertical line for VBLANK stop
VBSTRT	H	1CC	W	A	Vertical line for VBLANK start

Note:

( V10 – 0 <- D10 – 0 ) Affects CSY pin if BLAKEN=1 and VSY pin if CSCBEN=1

See BEAMCON0

VPOSR

Name	Rev	Addr	Type	Chip	Description
VPOSR	p	004	R	A	Read vertical most significant Bits ( and frame flop )
VPOSW		02A	W	A	Write most significant Bits ( and frame flop )

LOF = Long frame ( auto toggle control bit in BPLCON0 )

I0-I6 Chip identitication:
8361	( Regular ) or 8370 ( Fat ) ( Agnus – NTSC )	=	10
8367	( PAL ) or 8371 ( Fat – PAL ) ( Agnus – PAL )	=	00
8372	( Fat – hr ) ( agnushr ), thru Rev 4	=	20 PAL, 30 NTSC
8372	( Fat – hr ) ( agnushr ), Rev 5	=	22 PAL, 31 NTSC
8372	( Alice ) thru Rev 2	=	22 PAL, 32 NTSC
8374	( Alice ) Rev 3 thru Rev 4	=	23 PAL, 33 NTSC

LOL = Long line bit. When low, it indicates short raster line.

V9, 10 — hires chips only ( 20, 30 identifiers )

VHPOSR

Name	Rev	Addr	Type	Chip	Description
VHPOSR		006	R	A	Read Vertical and Horizontal position of beam, or lightpen
VHPOSW		02C	W	A	Write Vertical and Horizontal position of beam, or lightpen

Bit#	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
USE	V7	V6	V5	V4	V3	V2	V1	V0	H8	H7	H6	H5	H4	H3	H2	H1

RESOLUTION = 1 / 160 of SCREEN WITH ( 280 nS )

VSSTOP

Name	Rev	Addr	Type	Chip	Description
VSSTOP	H	1CA	W	A	Vertical position for VSYNC start
VTOTAL	H	1C(	W	A	Highest numbered Vertical line ( VARBEAMEN = 1 )

It`s the line number to reset the counter, so there`s this many + 1 in a field.

The exception is if the LACE bit is set ( BPLCON0 ), in which case every other field is this many + 2 and the short field is this many + 1.

Menu

ADKCON

AUDxLCH

AUDxLCL

AUDxLEN

AUDxPER

AUDxVOL

AUDxDAT

BEAMCON0

BLTxPTH

BLTxPTL

BLTxMOD

BLTAFWM

BLTALWM

BLTxDAT

BLTDDAT

BLTSIZE

BLTCON0

BLTSIZH

BLTSIZV

BPLHDAT

BPLHMOD

BPLHPTH

BPLHPTL

BPLHSTOP

BPLHSTRT

BPLxPTH

BPLxPTL

BPLxDAT

BPLxMOD

BPLCON0

BPLCON1

BPLCON2

BPLCON3

BPLCON4

CLXCON

CLXCON2

CLXDAT

COLORxx

COPCON

COPJMP1

COPJMP2

COP1LCH

COPINS

DDFSTRT

DIWSTRT

DIWHIGH

DMACON

DSKPTH

DSKLEN

DSKDAT

DSKDATR

DSKBYTR

DSKSYNC

FMODE

HBSTOP

HCENTER

HHPOSR

HSSTOP

HSSTRT

HTOTAL

INTENA

JOYxDAT

JOYTEST

LISAID

POTxDAT

POTGO

POTINP

REFPTR

SERDAT

SERDATR

SERPER

SPRHDAT

SPRHPTH

SPRHSTOP

SPRHSTRT

SPRxPTH

SPRxPOS

SPRxCTL

SPRxDAT