Rotate

This table indicates the number of clock periods for the shift and rotate instructions. The number of read and write cycles is shown in parenthesis as (r/w). The number of clock periods and the number of read and write cycles must be added respectively to those of the effective address calculation where indicated.

Shift/Rotate Instruction Execution Times

 Instruction  Size  Register  Memory
 ASR,ASL  byte,word  6 + 2n ( 1 / 0 )  8 ( 1 / 1 ) +
       long  8 + 2n ( 1 / 0 )  –
 LSR,LSL  byte,word  6 + 2n ( 1 / 0)  8 ( 1 / 1 ) +
       long  8 + 2n ( 1 / 0 )  –
 ROR,ROL  byte,word  6 + 2n ( 1 / 0 )  8 ( 1 / 1 ) +
       long  8 + 2n ( 1 / 0 )  –
 ROXR,ROXL  byte,word  6 + 2n ( 1 / 0 )  8 ( 1 / 1 ) +
       long  8 + 2n ( 1 / 0)  –

   +  Add effective address calculation time
   n  Is the shift or rotate count