This table indicates the number of clock periods for exception processing. The number of clock periods includes the time for all stacking, the vector fetch and the fetch of the first two instruction words of the handler routine. The number of bus read and write cycles is shown in parenthesis as (r/w).
Exception Processing Execution Times
| Exception | Periods |
| address error | 50 ( 4 / 7 ) |
| bus error | 50 ( 4 / 7 ) |
| CHK instruction ( trap taken ) | 44 ( 5 / 3 ) + |
| Divide by Zero | 42 ( 5 / 3 ) |
| illegal instruction | 34 ( 4 / 3 ) |
| interrupt | 44 ( 5 / 3 ) * |
| privilege violation | 34 ( 4 / 3 ) |
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| RESET ** | 40 ( 6 / 0 ) |
| trace | 34 ( 4 / 3 ) |
| TRAP instruction | 38 ( 4 / 3 ) |
| TRAPV instruction ( trap taken ) | 34 ( 4 / 3 ) |
| + | = | Add effective address calculation time. |
| * | = | The interrupt acknowledge cycle is assumed to take four clock periods. |
| ** | = | Indicates the time from when RESET and HALT are first sampled as negated to when instruction execution starts . |